M. Feser KBS GmbH
Date: 10.01.2025

This patch adds the devicetree for PTF-SUB3
-------------------------------------------------------------------------
diff -ruPN a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
--- a/arch/arm/boot/dts/am33xx.dtsi	2025-01-09 13:28:51.000000000 +0100
+++ b/arch/arm/boot/dts/am33xx.dtsi	2025-01-10 12:20:25.763944409 +0100
@@ -607,7 +607,7 @@
 			};
 		};
 
-		target-module@56000000 {
+		gfx: target-module@56000000 {
 			compatible = "ti,sysc-omap4", "ti,sysc";
 			reg = <0x5600fe00 0x4>,
 			      <0x5600fe10 0x4>;
diff -ruPN a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
--- a/arch/arm/boot/dts/am33xx-l4.dtsi	2025-01-09 13:28:51.000000000 +0100
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi	2025-01-10 12:20:25.763944409 +0100
@@ -1431,7 +1431,7 @@
 			};
 		};
 
-		target-module@4c000 {			/* 0x4804c000, ap 32 36.0 */
+		gpio1_target: target-module@4c000 {			/* 0x4804c000, ap 32 36.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
 			reg = <0x4c000 0x4>,
 			      <0x4c010 0x4>,
@@ -1834,7 +1834,7 @@
 			};
 		};
 
-		target-module@ac000 {			/* 0x481ac000, ap 54 38.0 */
+		gpio2_target: target-module@ac000 {			/* 0x481ac000, ap 54 38.0 */
 			compatible = "ti,sysc-omap2", "ti,sysc";
 			reg = <0xac000 0x4>,
 			      <0xac010 0x4>,
diff -ruPN a/arch/arm/boot/dts/sub3.dts b/arch/arm/boot/dts/sub3.dts
--- a/arch/arm/boot/dts/sub3.dts	1970-01-01 01:00:00.000000000 +0100
+++ b/arch/arm/boot/dts/sub3.dts	2025-01-10 12:36:16.170441055 +0100
@@ -0,0 +1,640 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PTF-SUB3 device tree
+ * Copyright (C) 2022 M. Feser
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+  model = "PTF-SUB3";
+  compatible = "kbs,sub3", "ti,am33xx";
+
+  cpus {
+    cpu@0 {
+      cpu0-supply = <&vdd1_reg>;
+    };
+  };
+
+  memory@80000000 {
+    device_type = "memory";
+    reg = <0x80000000 0x20000000>; // 512 MB
+  };
+    
+  vbat: fixedregulator0 {
+    compatible = "regulator-fixed";
+    regulator-name = "vbat";
+    regulator-min-microvolt = <5000000>;
+    regulator-max-microvolt = <5000000>;
+    regulator-always-on;
+  };
+
+  ldo33: fixedregulator1 {
+    compatible = "regulator-fixed";
+    regulator-name = "ldo33";
+    regulator-min-microvolt = <3300000>;
+    regulator-max-microvolt = <3300000>;
+    regulator-always-on;
+  };
+
+  switches {
+    compatible = "gpio-keys-polled";
+    pinctrl-names = "default";
+    pinctrl-0 = <&switch_pins>;
+    poll-interval = <100>;
+    
+    switch-mode0 {
+      label = "mode0";
+      linux,code = <1>; // Key = ESC
+      gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+    };
+  };
+
+  leds {
+    compatible = "gpio-leds";
+    pinctrl-names = "default";
+    pinctrl-0 = <&led_pins>;
+
+    led-green1 {
+      label = "green1";
+      gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+      linux,default-trigger = "heartbeat";
+      default-state = "off";
+    };
+    
+    led-green2 {
+      label = "green2";
+      gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+      default-state = "off";
+    };
+
+    led-red1 {
+      label = "red1";
+      gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+      default-state = "off";
+    };
+    
+    led-red2 {
+      label = "red2";
+      gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+      default-state = "off";
+    };
+  };
+  
+  spi1_mux_switch {
+    compatible = "mux-switch";
+    pinctrl-names = "default", "swd";
+    pinctrl-0 = <&spi1_pins>;
+    pinctrl-1 = <&swd_pins>;
+    status = "okay";
+  };
+  
+  slot0_mux_switch {
+    compatible = "mux-switch";
+    pinctrl-names = "default";
+    pinctrl-0 = <&slot0_default_pins>;
+    status = "okay";
+  };
+  
+  slot1_mux_switch {
+    compatible = "mux-switch";
+    pinctrl-names = "default";
+    pinctrl-0 = <&slot1_default_pins>;
+    status = "okay";
+  };
+  
+  slot2_mux_switch {
+    compatible = "mux-switch";
+    pinctrl-names = "default";
+    pinctrl-0 = <&slot2_default_pins>;
+    status = "okay";
+  };
+};
+
+&am33xx_pinmux {
+  pinctrl-names = "default";
+  pinctrl-0 = <&sysboot_pins &general_pins &ptfmcu_pins>;
+
+  sysboot_pins: pinmux_sysboot_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x8A0, PIN_OUTPUT, MUX_MODE7)  // lcd_data0.gpio2_6 -> FAN_CTRL
+      AM33XX_PADCONF(0x8D8, PIN_OUTPUT, MUX_MODE7)  // lcd_data14.gpio0_10 -> DBG0
+      AM33XX_PADCONF(0x8DC, PIN_OUTPUT, MUX_MODE7)  // lcd_data15.gpio0_11 -> DBG1
+      AM33XX_PADCONF(0xA1C, PIN_OUTPUT, MUX_MODE7)  // usb0_drvvbus.gpio0_18 -> SYSBOOT_DIS
+    >;
+  };
+  
+  general_pins: pinmux_general_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x844, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_a1.gpio1_17 -> RS232_STATUS
+      AM33XX_PADCONF(0x87C, PIN_OUTPUT, MUX_MODE7)        // gpmc_csn0.gpio1_29 -> EMMC_NRST
+      AM33XX_PADCONF(0x918, PIN_INPUT_PULLUP, MUX_MODE7)  // mii1_rx_dv.gpio3_4 -> PMIC_INT
+      AM33XX_PADCONF(0x9A0, PIN_INPUT_PULLUP, MUX_MODE7)  // mcasp0_aclkr.gpio3_18 -> FAN_TACH
+    >;
+  };
+  
+  ptfmcu_pins: ptfmcu_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x858, PIN_OUTPUT, MUX_MODE7)          // gpmc_a6.gpio1_22 -> PTF_MCU_SWD_WRN
+      AM33XX_PADCONF(0x85C, PIN_OUTPUT, MUX_MODE7)          // gpmc_a7.gpio1_23 -> PTF_MCU_RSTN
+      AM33XX_PADCONF(0x860, PIN_OUTPUT, MUX_MODE7)          // gpmc_a8.gpio1_24 -> PTF_MCU_IPC_RDY
+      AM33XX_PADCONF(0x864, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a9.gpio1_25 -> PTF_MCU_IPC_REQ
+      AM33XX_PADCONF(0x878, PIN_OUTPUT, MUX_MODE7)          // gpmc_ben1.gpio1_28 -> PTF_MCU_SWD_ENAN
+    >;
+  };
+  
+  switch_pins: pinmux_switch_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x8A8, PIN_INPUT, MUX_MODE7)   // lcd_data2.gpio2_8 -> MODE0
+    >;
+  };
+  
+  led_pins: pinmux_led_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x8C8, PIN_OUTPUT, MUX_MODE7)  // lcd_data10.gpio2_16
+      AM33XX_PADCONF(0x8CC, PIN_OUTPUT, MUX_MODE7)  // lcd_data11.gpio2_17
+      AM33XX_PADCONF(0x8D0, PIN_OUTPUT, MUX_MODE7)  // lcd_data12.gpio0_8
+      AM33XX_PADCONF(0x8D4, PIN_OUTPUT, MUX_MODE7)  // lcd_data13.gpio0_9
+    >;
+  };
+
+  i2c0_pins: pinmux_i2c0_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x988, PIN_INPUT_PULLUP, MUX_MODE0)  // i2c0_sda.i2c0_sda
+      AM33XX_PADCONF(0x98c, PIN_INPUT_PULLUP, MUX_MODE0)  // i2c0_scl.i2c0_scl
+    >;
+  };
+  
+  i2c1_pins: pinmux_i2c1_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x968, PIN_INPUT_PULLUP, MUX_MODE0)  // uart0_ctsn.i2c1_sda
+      AM33XX_PADCONF(0x96C, PIN_INPUT_PULLUP, MUX_MODE0)  // uart0_rtsn.i2c1_scl
+    >;
+  };
+
+  spi0_pins: pinmux_spi0_pins {
+    pinctrl-single,pins = <
+      // SPI clock pin has to be configured in rx active mode !
+      AM33XX_PADCONF(0x950, PIN_INPUT_PULLUP, MUX_MODE0)    // spi0_sclk.spi0_sclk
+      AM33XX_PADCONF(0x954, PIN_INPUT_PULLDOWN, MUX_MODE0)  // spi0_d0.spi0_d0 -> MISO
+      AM33XX_PADCONF(0x958, PIN_OUTPUT, MUX_MODE0)          // spi0_d1.spi0_d1 -> MOSI
+      AM33XX_PADCONF(0x95C, PIN_OUTPUT, MUX_MODE0)          // spi0_cs0.spi0_cs0 -> SPI0_CS0
+    >;
+  };
+  
+  spi1_pins: pinmux_spi1_pins {
+    pinctrl-single,pins = <
+      // SPI clock pin has to be configured in rx active mode !
+      AM33XX_PADCONF(0x990, PIN_INPUT_PULLUP, MUX_MODE3)    // mcasp0_aclkx.spi1_sclk
+      AM33XX_PADCONF(0x994, PIN_INPUT_PULLDOWN, MUX_MODE3)  // mcasp0_fsx.spi1_d0 -> MISO
+      AM33XX_PADCONF(0x998, PIN_OUTPUT, MUX_MODE3)          // mcasp0.axr0.spi1_d1 -> MOSI
+    >;
+  };
+  
+  spi1_cs_pins: pinmux_spi1cs_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x8E8, PIN_OUTPUT, MUX_MODE7)  // lcd_pclk.gpio2_24 -> SPI1_CS0
+      AM33XX_PADCONF(0x8E0, PIN_OUTPUT, MUX_MODE7)  // lcd_vsync.gpio2_22 -> SPI1_CS1
+      AM33XX_PADCONF(0x8E4, PIN_OUTPUT, MUX_MODE7)  // lcd_hsync.gpio2_23 -> SPI1_CS2
+      AM33XX_PADCONF(0x8EC, PIN_OUTPUT, MUX_MODE7)  // lcd_ac_bias_en.gpio2_25 -> SPI1_CS3
+     >;
+  };     
+  
+  swd_pins: pinmux_swd_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x990, PIN_OUTPUT, MUX_MODE7)          // mcasp0_aclkx.gpio3_14 -> CLK
+      AM33XX_PADCONF(0x994, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mcasp0_fsx.gpio3_15 -> MISO
+      AM33XX_PADCONF(0x998, PIN_OUTPUT, MUX_MODE7)          // mcasp0.axr0.gpio3_16 -> MOSI
+    >;
+  };
+  
+  uart0_pins: pinmux_uart0_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x970, PIN_INPUT_PULLUP, MUX_MODE0)   // uart0_rxd.uart0_rxd
+      AM33XX_PADCONF(0x974, PIN_OUTPUT, MUX_MODE0)         // uart0_txd.uart0_txd
+    >;
+  };
+  
+  uart1_pins: pinmux_uart1_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x980, PIN_INPUT_PULLUP, MUX_MODE0)   // uart1_rxd.uart1_rxd
+      AM33XX_PADCONF(0x984, PIN_OUTPUT, MUX_MODE0)         // uart1_txd.uart1_txd
+    >;
+  };
+  
+  uart2_pins: pinmux_uart2_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x92C, PIN_INPUT_PULLUP, MUX_MODE1)   // mii1_tx_clk.uart2_rxd
+      AM33XX_PADCONF(0x930, PIN_OUTPUT, MUX_MODE1)         // mii1_rx_clk.uart2_txd
+    >;
+  };
+  
+  uart3_pins: pinmux_uart3_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x934, PIN_INPUT_PULLUP, MUX_MODE1)   // mii1_rxd3.uart3_rxd
+      AM33XX_PADCONF(0x938, PIN_OUTPUT, MUX_MODE1)         // mii1_rxd2.uart3_txd
+    >;
+  };
+  
+  uart4_pins: pinmux_uart4_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x91C, PIN_INPUT_PULLUP, MUX_MODE3)   // mii1_txd3.uart4_rxd
+      AM33XX_PADCONF(0x920, PIN_OUTPUT, MUX_MODE3)         // mii1_txd2.uart4_txd
+    >;
+  };
+  
+  uart5_pins: pinmux_uart5_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x8C4, PIN_INPUT_PULLUP, MUX_MODE4)   // lcd_data9.uart5_rxd
+      AM33XX_PADCONF(0x8C0, PIN_OUTPUT, MUX_MODE4)         // lcd_data8.uart5_txd
+    >;
+  };
+
+  cpsw_default: cpsw_default {
+    pinctrl-single,pins = <
+      // ETH 1
+      AM33XX_PADCONF(0x90C, PIN_INPUT, MUX_MODE1)    // mii1_crs.rmii1_crs_dv
+      AM33XX_PADCONF(0x910, PIN_INPUT, MUX_MODE1)    // mii1_rxer.rmii1_rxer
+      AM33XX_PADCONF(0x914, PIN_OUTPUT, MUX_MODE1)   // mii1_txen.rmii1_txen
+      AM33XX_PADCONF(0x924, PIN_OUTPUT, MUX_MODE1)   // mii1_txd1.rmii1_txd1
+      AM33XX_PADCONF(0x928, PIN_OUTPUT, MUX_MODE1)   // mii1_txd0.rmii1_txd0
+      AM33XX_PADCONF(0x93C, PIN_INPUT, MUX_MODE1)    // mii1_rxd1.rmii1_rxd1
+      AM33XX_PADCONF(0x940, PIN_INPUT, MUX_MODE1)    // mii1_rxd0.rmii1_rxd0
+      AM33XX_PADCONF(0x944, PIN_INPUT_PULLDOWN, MUX_MODE0) // rmii1_refclk.rmii1_refclk
+
+      // ETH 2
+      AM33XX_PADCONF(0x870, PIN_INPUT, MUX_MODE3)    // gpmc_wait0.rmii2_crs_dv
+      AM33XX_PADCONF(0x874, PIN_INPUT, MUX_MODE3)    // gpmc_wpn.rmii2_rxer
+      AM33XX_PADCONF(0x840, PIN_OUTPUT, MUX_MODE3)   // gpmc_a0.rmii2_txen
+      AM33XX_PADCONF(0x850, PIN_OUTPUT, MUX_MODE3)   // gpmc_a4.rmii2_txd1
+      AM33XX_PADCONF(0x854, PIN_OUTPUT, MUX_MODE3)   // gpmc_a5.rmii2_txd0
+      AM33XX_PADCONF(0x868, PIN_INPUT, MUX_MODE3)    // gpmc_a10.rmii2_rxd1
+      AM33XX_PADCONF(0x86C, PIN_INPUT, MUX_MODE3)    // gpmc_a11.rmii2_rxd0
+      AM33XX_PADCONF(0x908, PIN_INPUT_PULLDOWN, MUX_MODE1) // mii1_col.rmii2_refclk
+    >;
+  };
+
+  cpsw_sleep: cpsw_sleep {
+    pinctrl-single,pins = <
+      // ETH 1 sleep
+      AM33XX_PADCONF(0x90C, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_crs.rmii1_crs_dv
+      AM33XX_PADCONF(0x910, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_rxer.rmii1_rxer
+      AM33XX_PADCONF(0x914, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_txen.rmii1_txen
+      AM33XX_PADCONF(0x924, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_txd1.rmii1_txd1
+      AM33XX_PADCONF(0x928, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_txd0.rmii1_txd0
+      AM33XX_PADCONF(0x93C, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_rxd1.rmii1_rxd1
+      AM33XX_PADCONF(0x940, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_rxd0.rmii1_rxd0
+      AM33XX_PADCONF(0x944, PIN_INPUT_PULLDOWN, MUX_MODE7)  // rmii1_refclk.rmii1_refclk
+
+      // ETH 2 sleep
+      AM33XX_PADCONF(0x870, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_wait0.rmii2_crs_dv
+      AM33XX_PADCONF(0x874, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_wpn.rmii2_rxer
+      AM33XX_PADCONF(0x840, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a0.rmii2_txen
+      AM33XX_PADCONF(0x850, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a4.rmii2_txd1
+      AM33XX_PADCONF(0x854, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a5.rmii2_txd0
+      AM33XX_PADCONF(0x868, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a10.rmii2_rxd1
+      AM33XX_PADCONF(0x86C, PIN_INPUT_PULLDOWN, MUX_MODE7)  // gpmc_a11.rmii2_rxd0
+      AM33XX_PADCONF(0x908, PIN_INPUT_PULLDOWN, MUX_MODE7)  // mii1_col.rmii2_refclk
+    >;
+  };
+
+  davinci_mdio_default: davinci_mdio_default {
+    pinctrl-single,pins = <
+      // MDIO
+      AM33XX_PADCONF(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)  // mdio_data.mdio_data
+      AM33XX_PADCONF(0x94C, PIN_OUTPUT_PULLUP, MUX_MODE0)                 // mdio_clk.mdio_clk
+    >;
+  };
+
+  davinci_mdio_sleep: davinci_mdio_sleep {
+    pinctrl-single,pins = <
+      // MDIO sleep
+      AM33XX_PADCONF(0x948, PIN_INPUT_PULLDOWN, MUX_MODE7)
+      AM33XX_PADCONF(0x94C, PIN_INPUT_PULLDOWN, MUX_MODE7)
+    >;
+  };
+
+  mmc1_pins: pinmux_mmc1_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)         // spi0_cs1.gpio0_6
+      AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
+      AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
+      AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
+      AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
+      AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
+      AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
+    >;
+  };
+
+  emmc_pins: pinmux_emmc_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x880, PIN_INPUT_PULLUP, MUX_MODE2) // gpmc_csn1.mmc1_clk
+      AM33XX_PADCONF(0x884, PIN_INPUT_PULLUP, MUX_MODE2) // gpmc_csn2.mmc1_cmd
+      AM33XX_PADCONF(0x800, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad0.mmc1_dat0
+      AM33XX_PADCONF(0x804, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad1.mmc1_dat1
+      AM33XX_PADCONF(0x808, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad2.mmc1_dat2
+      AM33XX_PADCONF(0x80c, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad3.mmc1_dat3
+      AM33XX_PADCONF(0x810, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad4.mmc1_dat4
+      AM33XX_PADCONF(0x814, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad5.mmc1_dat5
+      AM33XX_PADCONF(0x818, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad6.mmc1_dat6
+      AM33XX_PADCONF(0x81c, PIN_INPUT_PULLUP, MUX_MODE1) // gpmc_ad7.mmc1_dat7
+    >;
+  };
+};
+
+#include "sub3-slots.dtsi"
+
+&gpio0_target {
+  ti,no-reset-on-init;
+};
+
+&gpio1_target {
+  ti,no-reset-on-init;
+};
+
+&gpio2_target {
+  ti,no-reset-on-init;
+};
+
+&gpio3_target {
+  ti,no-reset-on-init;
+};
+
+&uart0 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart0_pins>;
+  status = "okay";
+};
+
+&uart1 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart1_pins>;
+  status = "okay";
+};
+
+&uart2 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart2_pins>;
+  status = "okay";
+};
+
+&uart3 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart3_pins>;
+  status = "okay";
+};
+
+&uart4 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart4_pins>;
+  status = "okay";
+};
+
+&uart5 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&uart5_pins>;
+  status = "okay";
+};
+
+&usb0 {
+	dr_mode = "peripheral";
+};
+
+&usb1_phy {
+	status = "disabled";
+};
+
+&usb1 {
+	status = "disabled";
+};
+
+&i2c0 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c0_pins>;
+
+  status = "okay";
+  clock-frequency = <400000>;
+
+  tps: tps@2d {
+    reg = <0x2d>;
+  };
+};
+
+&i2c1 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c1_pins>;
+
+  status = "okay";
+  clock-frequency = <400000>;
+};
+
+&spi0 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&spi0_pins>;
+  ti,spi-num-cs = <1>;
+  cs-gpios = <0>;
+  status = "okay";
+  
+  spidev0@0 {
+    compatible = "linux,spidev";
+    reg = <0>;
+    spi-max-frequency = <10000000>;
+  };
+};
+
+&spi1 {
+  pinctrl-names = "default";
+  pinctrl-0 = <&spi1_cs_pins>;
+  ti,spi-num-cs = <4>;
+  cs-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>, <&gpio2 22 GPIO_ACTIVE_LOW>, 
+             <&gpio2 23 GPIO_ACTIVE_LOW>, <&gpio2 25 GPIO_ACTIVE_LOW>;
+  status = "okay";
+  
+  sysnvm@0 {
+    compatible = "atmel,at25";
+    reg = <0>;
+    spi-max-frequency = <10000000>;
+
+    pagesize = <32>;
+    size = <8192>;
+    address-width = <16>;
+  };
+  
+  ptfmcu@1 {
+    compatible = "linux,spidev";
+    reg = <1>;
+    spi-max-frequency = <10000000>;
+  };
+  
+  slot0spidev@2 {
+    compatible = "linux,spidev";
+    reg = <2>;
+    spi-max-frequency = <10000000>;
+  };
+  
+  slot1spidev@3 {
+    compatible = "linux,spidev";
+    reg = <3>;
+    spi-max-frequency = <10000000>;
+  };
+};
+
+&tscadc {
+  status = "okay";
+  adc {
+    ti,adc-channels = <0 1 2 3 4 5 6 7>;
+  };
+};
+
+&cpsw_emac0 {
+  phy-handle = <&ethernetphy0>;
+  phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+  phy-handle = <&ethernetphy1>;
+  phy-mode = "rmii";
+};
+
+&mac {
+  pinctrl-names = "default", "sleep";
+  pinctrl-0 = <&cpsw_default>;
+  pinctrl-1 = <&cpsw_sleep>;
+  status = "okay";
+};
+
+&davinci_mdio {
+  pinctrl-names = "default", "sleep";
+  pinctrl-0 = <&davinci_mdio_default>;
+  pinctrl-1 = <&davinci_mdio_sleep>;
+  status = "okay";
+
+  ethernetphy0: ethernet-phy@1 {
+    reg = <1>;
+    smsc,disable-energy-detect;
+  };
+  
+  ethernetphy1: ethernet-phy@2 {
+    reg = <2>;
+    smsc,disable-energy-detect;
+  };
+};
+
+&mmc1 {
+  vmmc-supply = <&vmmc_reg>;
+  vqmmc-supply = <&vmmc_reg>;
+  pinctrl-names = "default";
+  pinctrl-0 = <&mmc1_pins>;
+  bus-width = <4>;
+  cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+  cd-debounce-delay-ms = <5>;
+  status = "okay";
+};
+
+&mmc2 {
+  vmmc-supply = <&ldo33>;
+  vqmmc-supply = <&ldo33>;
+  pinctrl-names = "default";
+  pinctrl-0 = <&emmc_pins>;
+  bus-width = <8>;
+  non-removable;
+  status = "okay";
+};
+
+&aes {
+	status = "okay";
+};
+
+&sham {
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&clk_32768_ck>;
+	clock-names = "ext-clk";
+};
+
+&gfx {
+	status = "disabled";
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+  vcc1-supply = <&vbat>;
+  vcc2-supply = <&vbat>;
+  vcc3-supply = <&vbat>;
+  vcc4-supply = <&vbat>;
+  vcc5-supply = <&vbat>;
+  vcc6-supply = <&vbat>;
+  vcc7-supply = <&vbat>;
+  vccio-supply = <&vbat>;
+
+  regulators {
+    vrtc_reg: regulator@0 {
+      regulator-always-on;
+    };
+
+    vio_reg: regulator@1 {
+      regulator-always-on;
+    };
+
+    vdd1_reg: regulator@2 {
+      // VDD_MPU voltage limits 0.950V - 1.325V with +/-4% tolerance
+      regulator-name = "vdd_mpu";
+      regulator-min-microvolt = <912500>;
+      regulator-max-microvolt = <1375000>;
+      regulator-boot-on;
+      regulator-always-on;
+    };
+
+    vdd2_reg: regulator@3 {
+      // VDD_CORE voltage limits 0.950V - 1.100V with +/-4% tolerance
+      regulator-name = "vdd_core";
+      regulator-min-microvolt = <912500>;
+      regulator-max-microvolt = <1137500>;
+      regulator-boot-on;
+      regulator-always-on;
+    };
+
+    vdd3_reg: regulator@4 {
+      regulator-always-on;
+    };
+
+    vdig1_reg: regulator@5 {
+      regulator-always-on;
+    };
+
+    vdig2_reg: regulator@6 {
+      regulator-always-on;
+    };
+
+    vpll_reg: regulator@7 {
+      regulator-always-on;
+    };
+
+    vdac_reg: regulator@8 {
+      regulator-always-on;
+    };
+
+    vaux1_reg: regulator@9 {
+      regulator-always-on;
+    };
+
+    vaux2_reg: regulator@10 {
+      regulator-always-on;
+    };
+
+    vaux33_reg: regulator@11 {
+      regulator-always-on;
+    };
+
+    vmmc_reg: regulator@12 {
+      regulator-min-microvolt = <1800000>;
+      regulator-max-microvolt = <3300000>;
+      regulator-always-on;
+    };
+  };
+};
diff -ruPN a/arch/arm/boot/dts/sub3-slots.dtsi b/arch/arm/boot/dts/sub3-slots.dtsi
--- a/arch/arm/boot/dts/sub3-slots.dtsi	1970-01-01 01:00:00.000000000 +0100
+++ b/arch/arm/boot/dts/sub3-slots.dtsi	2025-01-08 09:59:05.916777000 +0100
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PTF-SUB3 slots device tree include
+ * Copyright (C) 2022 M. Feser
+ */
+
+&am33xx_pinmux {
+// Slot 0
+  slot0_default_pins: pinmux_slot0_default_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x890, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_advn_ale.gpio2_2 -> GPIO_00
+      AM33XX_PADCONF(0x89C, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ben0_cle.gpio2_5 -> GPIO_01
+      AM33XX_PADCONF(0x848, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_a2.gpio1_18 -> GPO_02
+      AM33XX_PADCONF(0x964, PIN_INPUT_PULLUP, MUX_MODE7)  // ecap0_in_pwm0_out.gpio0_7 -> GPIO_03
+      AM33XX_PADCONF(0x9B0, PIN_INPUT_PULLUP, MUX_MODE7)  // xdma_event_intr0.gpio0_19 -> GPIO_04
+      AM33XX_PADCONF(0x8A4, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data1.gpio2_7 -> GPO_05
+      AM33XX_PADCONF(0x8AC, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data3.gpio2_9 -> GPO_06
+      AM33XX_PADCONF(0x8B0, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data4.gpio2_10 -> GPO_07
+
+    >;
+  };
+
+// Slot 1
+  slot1_default_pins: pinmux_slot1_default_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x898, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_wen.gpio2_4 -> GPIO_10
+      AM33XX_PADCONF(0x894, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_oen_ren.gpio2_3 -> GPIO_11
+      AM33XX_PADCONF(0x84C, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_a3.gpio1_19 -> GPIO_12
+      AM33XX_PADCONF(0x99C, PIN_INPUT_PULLUP, MUX_MODE7)  // mcasp0_ahclkr.gpio3_17 -> GPIO_13
+      AM33XX_PADCONF(0x9B4, PIN_INPUT_PULLUP, MUX_MODE7)  // xdma_event_intr1.gpio0_20 -> GPIO_14
+      AM33XX_PADCONF(0x8B4, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data5.gpio2_11 -> GPO_15
+      AM33XX_PADCONF(0x8B8, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data6.gpio2_12 -> GPO_16
+      AM33XX_PADCONF(0x8BC, PIN_INPUT_PULLUP, MUX_MODE7)  // lcd_data7.gpio2_13 -> GPO_17
+    >;
+  };
+  
+// Slot 2
+  slot2_default_pins: pinmux_slot2_default_pins {
+    pinctrl-single,pins = <
+      AM33XX_PADCONF(0x88C, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_clk.mmc2_clk
+      AM33XX_PADCONF(0x888, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_csn3.mmc2_cmd
+      AM33XX_PADCONF(0x830, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad12.mmc2_dat0
+      AM33XX_PADCONF(0x834, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad13.mmc2_dat1
+      AM33XX_PADCONF(0x838, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad14.mmc2_dat2
+      AM33XX_PADCONF(0x83C, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad15.mmc2_dat3
+      AM33XX_PADCONF(0x820, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad8.mmc2_dat4
+      AM33XX_PADCONF(0x824, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad9.mmc2_dat5
+      AM33XX_PADCONF(0x828, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad10.mmc2_dat6
+      AM33XX_PADCONF(0x82C, PIN_INPUT_PULLUP, MUX_MODE7)  // gpmc_ad11.mmc2_dat7
+      AM33XX_PADCONF(0xA34, PIN_INPUT_PULLUP, MUX_MODE7)  // usb1_drvvbus.gpio3_13
+    >;
+  };
+};