M. Feser KBS GmbH Date: 15.09.2022 This patch adds the support for PTF-MIU ------------------------------------------------------------------------- diff -ruPN a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile --- a/arch/arm/boards/Makefile 2022-08-10 08:49:07.000000000 +0200 +++ b/arch/arm/boards/Makefile 2022-09-13 07:30:45.850925044 +0200 @@ -16,6 +16,7 @@ obj-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek/ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ +obj-$(CONFIG_MACH_MIU) += miu/ obj-$(CONFIG_MACH_CANON_A1100) += canon-a1100/ obj-$(CONFIG_MACH_CM_FX6) += cm-fx6/ obj-$(CONFIG_MACH_NITROGEN6) += boundarydevices-nitrogen6/ diff -ruPN a/arch/arm/boards/miu/board.c b/arch/arm/boards/miu/board.c --- a/arch/arm/boards/miu/board.c 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/board.c 2022-09-13 08:50:57.383452272 +0200 @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PTF-MIU board support + * Copyright (C) 2022 J. Kneipp + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPI0_CLK GPIO_NR(0, 2) +#define SPI0_MOSI GPIO_NR(0, 4) +#define SEG_STROBE GPIO_NR(2, 8) + +#define GPIO_NR(bank,pin) (bank*32 + pin) + +static int miu_coredevice_init(void) +{ + if (!of_machine_is_compatible("kbs,miu")) + return 0; + + am33xx_register_ethaddr(0, 0); + return 0; +} +coredevice_initcall(miu_coredevice_init); + +static int miu_mem_init(void) +{ + if (!of_machine_is_compatible("kbs,miu")) + return 0; + + arm_add_mem_device("ram0", 0x80000000, SZ_512M); + return 0; +} +mem_initcall(miu_mem_init); + +static int miu_devices_init(void) +{ + int i,seg; + + if (!of_machine_is_compatible("kbs,miu")) + return 0; + + // Initialize all chipselect outputs to high state + gpio_direction_output(GPIO_NR(1, 18), 1); + gpio_direction_output(GPIO_NR(1, 19), 1); + for (i=6; i<14; i++) + gpio_direction_output(GPIO_NR(2, i), 1); + + // Initialize reset outputs to high state + gpio_direction_output(GPIO_NR(0, 10), 1); + gpio_direction_output(GPIO_NR(0, 11), 1); + + // 7seg = "--" + gpio_direction_output(SPI0_CLK, 0); + gpio_direction_output(SPI0_MOSI, 0); + gpio_direction_output(SEG_STROBE, 0); + seg = 0x0202; + for (i=0; i<16; i++) + { + gpio_set_value(SPI0_MOSI, (seg & 0x0001)); + gpio_set_value(SPI0_CLK, 1); + gpio_set_value(SPI0_CLK, 0); + seg >>= 1; + } + gpio_set_value(SEG_STROBE, 1); + + // Release SYSBOOT + gpio_direction_output(GPIO_NR(0, 18), 1); + + if (bootsource_get() == BOOTSOURCE_MMC) { + if (bootsource_get_instance() == 0) + omap_set_bootmmc_devname("mmc0"); + else + omap_set_bootmmc_devname("mmc1"); + } + + defaultenv_append_directory(defaultenv_miu); + armlinux_set_architecture(MACH_TYPE_TAM335X); + + if (IS_ENABLED(CONFIG_SHELL_NONE)) + return am33xx_of_register_bootdevice(); + + return 0; +} +coredevice_initcall(miu_devices_init); diff -ruPN a/arch/arm/boards/miu/defaultenv-miu/boot/mmc b/arch/arm/boards/miu/defaultenv-miu/boot/mmc --- a/arch/arm/boards/miu/defaultenv-miu/boot/mmc 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/defaultenv-miu/boot/mmc 2022-09-02 11:58:11.857844000 +0200 @@ -0,0 +1,8 @@ +#!/bin/sh + +global.bootm.image=/boot/zImage +global.bootm.oftree=/boot/oftree +if [ -f "/boot/initramfs.igz" ]; then + global.bootm.initrd=/boot/initramfs.igz +fi +global.linux.bootargs.dyn.root="root=/dev/mmcblk${bootsource_instance}p2 rootfstype=ext4 rootwait quiet rstsrc=${global.system.reset}" diff -ruPN a/arch/arm/boards/miu/defaultenv-miu/nv/autoboot_timeout b/arch/arm/boards/miu/defaultenv-miu/nv/autoboot_timeout --- a/arch/arm/boards/miu/defaultenv-miu/nv/autoboot_timeout 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/defaultenv-miu/nv/autoboot_timeout 2022-09-02 11:58:11.857844000 +0200 @@ -0,0 +1 @@ +0 diff -ruPN a/arch/arm/boards/miu/defaultenv-miu/nv/boot.default b/arch/arm/boards/miu/defaultenv-miu/nv/boot.default --- a/arch/arm/boards/miu/defaultenv-miu/nv/boot.default 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/defaultenv-miu/nv/boot.default 2022-09-02 11:58:11.857844000 +0200 @@ -0,0 +1 @@ +mmc diff -ruPN a/arch/arm/boards/miu/lowlevel.c b/arch/arm/boards/miu/lowlevel.c --- a/arch/arm/boards/miu/lowlevel.c 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/lowlevel.c 2022-09-13 11:56:48.897568460 +0200 @@ -0,0 +1,212 @@ + // SPDX-License-Identifier: GPL-2.0-only +/* + * PTF-MIU low-level board support + * Copyright (C) 2022 J. Kneipp + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AM33XX_PRM_RSTTIME (AM33XX_PRM_BASE + 0x0F04) + +#define RAM_BASE_ADDR 0x80000000 +#define RAM_SIZE 0x20000000 + +#define INIT_LEDS() { \ + *((uint32_t*)0x44E00408) = 0x00040002; \ + *((uint32_t*)0x44E07134) &= ~((1<<8) + (1<<9)); \ +} + +#define LED_B_ON() *((uint32_t*)0x44E07194) = (1<<8) +#define LED_B_OFF() *((uint32_t*)0x44E07190) = (1<<8) +#define LED_R_ON() *((uint32_t*)0x44E07194) = (1<<9) +#define LED_R_OFF() *((uint32_t*)0x44E07190) = (1<<9) + +static const struct am33xx_ddr_data ddr3_data = { + .rd_slave_ratio0 = 0x38, + .wr_dqs_slave_ratio0 = 0x44, + .fifo_we_slave_ratio0 = 0x94, + .wr_slave_ratio0 = 0x7D, + .use_rank0_delay = 0x01, + .dll_lock_diff0 = 0x0, +}; + +static const struct am33xx_cmd_control ddr3_cmd_ctrl = { + .slave_ratio0 = 0x80, + .dll_lock_diff0 = 0x1, + .invert_clkout0 = 0x0, + .slave_ratio1 = 0x80, + .dll_lock_diff1 = 0x1, + .invert_clkout1 = 0x0, + .slave_ratio2 = 0x80, + .dll_lock_diff2 = 0x1, + .invert_clkout2 = 0x0, +}; + +static const struct am33xx_emif_regs ddr3_regs = { + .emif_read_latency = 0x100007, + .emif_tim1 = 0x0AAAD4DB, + .emif_tim2 = 0x266B7FDA, + .emif_tim3 = 0x501F867F, + .ocp_config = 0x003D3D3D, + .zq_config = 0x50074BE4, + .sdram_config = 0x61C05332, + .sdram_config2 = 0x0, + .sdram_ref_ctrl = 0xC30, +}; + +extern char __dtb_z_miu_start[]; + +#ifdef MLO_RAMTEST +static void ram_test_error(void) +{ + volatile uint32_t cnt; + LED_B_OFF(); + while (1) + { + LED_R_ON(); + for (cnt=0; cnt<200000; cnt++) {}; + LED_R_OFF(); + for (cnt=0; cnt<200000; cnt++) {}; + } +} + +static void ram_test_data_pattern(const uint16_t pattern) +{ + volatile uint16_t data; + + // Write pattern, clear bus and read back data + *((volatile uint16_t*)RAM_BASE_ADDR) = pattern; + *((volatile uint16_t*)(RAM_BASE_ADDR+2)) = ~pattern; + data = *((volatile uint16_t*)RAM_BASE_ADDR); + if (data != pattern) + { + printf("ERROR (pattern: 0x%04X, read: 0x%04X)\r\n", pattern, data); + ram_test_error(); + } +} + +static void ram_test(void) +{ + uint16_t pattern; + uint8_t byteData; + uint32_t wordData; + volatile uint8_t* byteAddr; + volatile uint32_t* wordAddr; + + INIT_LEDS(); + LED_B_ON(); + + printf("\r\n\r\nPerforming RAM test\r\n"); + printf("Data lines (walking one)\r\n"); + for (pattern=0x0001; pattern>0; ) + { + ram_test_data_pattern(pattern); + pattern <<= 1; + } + + printf("Data lines (walking zero)\r\n"); + for (pattern=0xFFFE; pattern<0xFFFF; ) + { + ram_test_data_pattern(pattern); + pattern <<= 1; + pattern |= 0x0001; + } + + printf("Address lines\r\n"); + printf("Setting data\r\n"); + for (byteAddr=(uint8_t*)RAM_BASE_ADDR; byteAddr<(uint8_t*)(RAM_BASE_ADDR+4); byteAddr++) + *byteAddr = (uint8_t)((uint32_t)byteAddr & 0x000000FF); + for (wordAddr=(uint32_t*)(RAM_BASE_ADDR+4); wordAddr<(uint32_t*)(RAM_BASE_ADDR+RAM_SIZE); wordAddr++) + *wordAddr = (uint32_t)wordAddr; + + printf("Checking data\r\n"); + for (byteAddr=(uint8_t*)RAM_BASE_ADDR; byteAddr<(uint8_t*)(RAM_BASE_ADDR+4); byteAddr++) + { + byteData = *byteAddr; + if (byteData != (uint8_t)((uint32_t)byteAddr & 0x000000FF)) + { + printf("ERROR (addr: 0x%08X, read: 0x%02X)\r\n", (uint32_t)byteAddr, byteData); + ram_test_error(); + } + } + for (wordAddr=(uint32_t*)(RAM_BASE_ADDR+4); wordAddr<(uint32_t*)(RAM_BASE_ADDR+RAM_SIZE); wordAddr++) + { + wordData = *wordAddr; + if (wordData != (uint32_t)wordAddr) + { + printf("ERROR (addr: 0x%08X, read: 0x%08X)\r\n", (uint32_t)wordAddr, wordData); + ram_test_error(); + } + } + + LED_B_OFF(); +} +#endif + +static noinline void miu_sram_init(void) +{ + void *fdt; + + fdt = __dtb_z_miu_start; + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + omap_watchdog_disable(IOMEM(AM33XX_WDT_BASE)); + + // Setup the PLLs and the clocks for the peripherals + am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_400); + + am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs, &ddr3_data); + + // Configure RSTTIME1 to maximum (~10us with 24MHz crystal) + __raw_writel(0x000010FF, AM33XX_PRM_RSTTIME); + + am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE); + am33xx_enable_uart0_pin_mux(); + omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + putc_ll('>'); + +#ifdef MLO_RAMTEST + ram_test(); +#endif + + am335x_barebox_entry(fdt); +} + +ENTRY_FUNCTION(start_miu_sram, bootinfo, r1, r2) +{ + am33xx_save_bootinfo((void *)bootinfo); + + /* + * Setup C environment, the board init code uses global variables. + * Stackpointer has already been initialized by the ROM code. + */ + relocate_to_current_adr(); + setup_c(); + + miu_sram_init(); +} + +ENTRY_FUNCTION(start_miu_sdram, r0, r1, r2) +{ + void *fdt; + + fdt = __dtb_z_miu_start + get_runtime_offset(); + am335x_barebox_entry(fdt); +} diff -ruPN a/arch/arm/boards/miu/Makefile b/arch/arm/boards/miu/Makefile --- a/arch/arm/boards/miu/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boards/miu/Makefile 2022-09-12 15:49:31.304510053 +0200 @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# PTF-MIU board support makefile +# Copyright (C) 2022 J. Kneipp +# + +lwl-y += lowlevel.o +obj-y += board.o +bbenv-y += defaultenv-miu diff -ruPN a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile --- a/arch/arm/dts/Makefile 2022-08-10 08:49:07.000000000 +0200 +++ b/arch/arm/dts/Makefile 2022-09-13 07:37:53.338802281 +0200 @@ -7,6 +7,7 @@ lwl-$(CONFIG_MACH_ADVANTECH_ROM_742X) += imx6dl-advantech-rom-7421.dtb.o lwl-$(CONFIG_MACH_AFI_GF) += am335x-afi-gf.dtb.o lwl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o +lwl-$(CONFIG_MACH_MIU) += miu.dtb.o lwl-$(CONFIG_MACH_CANON_A1100) += canon-a1100.dtb.o lwl-$(CONFIG_MACH_CLEP7212) += ep7212-clep7212.dtb.o lwl-$(CONFIG_MACH_CM_FX6) += imx6dl-cm-fx6.dtb.o imx6q-cm-fx6.dtb.o imx6q-utilite.dtb.o diff -ruPN a/arch/arm/dts/miu.dts b/arch/arm/dts/miu.dts --- a/arch/arm/dts/miu.dts 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/dts/miu.dts 2022-09-13 08:32:30.062352197 +0200 @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PTF-MIU device tree + * Copyright (C) 2022 M. Feser + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "PTF-MIU"; + compatible = "kbs,miu", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; // 512 MB + }; + + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + ldo33: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "ldo33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-blue { + label = "blue"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-red { + label = "red"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&sysboot_pins &slot_pins &spi0_bb_pins>; + + sysboot_pins: pinmux_sysboot_pins { + pinctrl-single,pins = < + 0x0A0 PIN_OUTPUT MUX_MODE7 // lcd_data0.gpio2_6 -> GPO_20 + 0x0A4 PIN_OUTPUT MUX_MODE7 // lcd_data1.gpio2_7 -> GPO_30 + 0x0A8 PIN_INPUT MUX_MODE7 // lcd_data2.gpio2_8 -> 7SEG_STROBE + 0x0AC PIN_OUTPUT MUX_MODE7 // lcd_data3.gpio2_9 -> SPI0_CS1 + 0x0B0 PIN_OUTPUT MUX_MODE7 // lcd_data4.gpio2_10 -> SPI1_CS0 + 0x0B4 PIN_OUTPUT MUX_MODE7 // lcd_data5.gpio2_11 -> SPI1_CS1 + 0x0B8 PIN_OUTPUT MUX_MODE7 // lcd_data6.gpio2_12 -> SPI1_CS2 + 0x0BC PIN_OUTPUT MUX_MODE7 // lcd_data7.gpio2_13 -> SPI1_CS3 + 0x0D8 PIN_OUTPUT MUX_MODE7 // lcd_data14.gpio0_10 -> EMMC_NRST + 0x0DC PIN_OUTPUT MUX_MODE7 // lcd_data15.gpio0_11 -> EXP_NRST + 0x21C PIN_OUTPUT MUX_MODE7 // usb0_drvvbus.gpio0_18 -> SYSBOOT_DIS + >; + }; + + slot_pins: pinmux_slot_pins { + pinctrl-single,pins = < + 0x048 PIN_OUTPUT MUX_MODE7 // gpmc_a2.gpio1_18 -> GPO_00 + 0x04C PIN_OUTPUT MUX_MODE7 // gpmc_a3.gpio1_19 -> GPO_10 + 0x164 PIN_INPUT_PULLUP MUX_MODE7 // ecap0_in_pwm0_out.gpio0_7 -> GPIO_02 + 0x19C PIN_INPUT_PULLUP MUX_MODE7 // mcasp0_ahclkr.gpio3_17 -> GPIO_12 + 0x044 PIN_INPUT_PULLUP MUX_MODE7 // gpmc_a1.gpio1_17 -> GPIO_22 + 0x0E8 PIN_INPUT_PULLUP MUX_MODE7 // lcd_pclk.gpio2_24 -> GPIO_32 + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + 0x0D0 PIN_OUTPUT MUX_MODE7 // lcd_data12.gpio0_8 + 0x0D4 PIN_OUTPUT MUX_MODE7 // lcd_data13.gpio0_9 + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 PIN_INPUT_PULLUP MUX_MODE0 // i2c0_sda.i2c0_sda + 0x18c PIN_INPUT_PULLUP MUX_MODE0 // i2c0_scl.i2c0_scl + >; + }; + + spi0_bb_pins: pinmux_spi0_bb_pins { + pinctrl-single,pins = < + 0x150 PIN_OUTPUT MUX_MODE7 // spi0_sclk.gpio0_2 -> CLK + 0x158 PIN_OUTPUT MUX_MODE7 // spi0_d1.gpio0_4 -> MOSI + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 PIN_INPUT_PULLUP MUX_MODE0 // uart0_rxd.uart0_rxd + 0x174 PIN_OUTPUT MUX_MODE0 // uart0_txd.uart0_txd + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + // ETH 1 + 0x10C PIN_INPUT MUX_MODE1 // mii1_crs.rmii1_crs_dv + 0x110 PIN_INPUT MUX_MODE1 // mii1_rxer.rmii1_rxer + 0x114 PIN_OUTPUT MUX_MODE1 // mii1_txen.rmii1_txen + 0x124 PIN_OUTPUT MUX_MODE1 // mii1_txd1.rmii1_txd1 + 0x128 PIN_OUTPUT MUX_MODE1 // mii1_txd0.rmii1_txd0 + 0x13C PIN_INPUT MUX_MODE1 // mii1_rxd1.rmii1_rxd1 + 0x140 PIN_INPUT MUX_MODE1 // mii1_rxd0.rmii1_rxd0 + 0x144 PIN_INPUT_PULLDOWN MUX_MODE0 // rmii1_refclk.rmii1_refclk + + // ETH 2 + 0x070 PIN_INPUT MUX_MODE3 // gpmc_wait0.rmii2_crs_dv + 0x074 PIN_INPUT MUX_MODE3 // gpmc_wpn.rmii2_rxer + 0x040 PIN_OUTPUT MUX_MODE3 // gpmc_a0.rmii2_txen + 0x050 PIN_OUTPUT MUX_MODE3 // gpmc_a4.rmii2_txd1 + 0x054 PIN_OUTPUT MUX_MODE3 // gpmc_a5.rmii2_txd0 + 0x068 PIN_INPUT MUX_MODE3 // gpmc_a10.rmii2_rxd1 + 0x06C PIN_INPUT MUX_MODE3 // gpmc_a11.rmii2_rxd0 + 0x108 PIN_INPUT_PULLDOWN MUX_MODE1 // mii1_col.rmii2_refclk + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + // MDIO + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST) MUX_MODE0 // mdio_data.mdio_data + 0x14C PIN_OUTPUT_PULLUP MUX_MODE0 // mdio_clk.mdio_clk + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 PIN_INPUT MUX_MODE7 // spi0_cs1.gpio0_6 + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 PIN_INPUT_PULLUP MUX_MODE2 // gpmc_csn1.mmc1_clk + 0x84 PIN_INPUT_PULLUP MUX_MODE2 // gpmc_csn2.mmc1_cmd + 0x00 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad0.mmc1_dat0 + 0x04 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad1.mmc1_dat1 + 0x08 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad2.mmc1_dat2 + 0x0c PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad3.mmc1_dat3 + 0x10 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad4.mmc1_dat4 + 0x14 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad5.mmc1_dat5 + 0x18 PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad6.mmc1_dat6 + 0x1c PIN_INPUT_PULLUP MUX_MODE1 // gpmc_ad7.mmc1_dat7 + >; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + }; +}; + +&cpsw_emac0 { + phy-handle = <ðernetphy0>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy-handle = <ðernetphy1>; + phy-mode = "rmii"; +}; + + + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; + + ethernetphy0: ethernet-phy@1 { + reg = <1>; + smsc,disable-energy-detect; + }; + + ethernetphy1: ethernet-phy@2 { + reg = <2>; + smsc,disable-energy-detect; + }; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <&ldo33>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + ti,non-removable; + status = "okay"; +}; + +#include + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + // VDD_MPU voltage limits 0.950V - 1.325V with +/-4% tolerance + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + // VDD_CORE voltage limits 0.950V - 1.100V with +/-4% tolerance + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1137500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff -ruPN a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig --- a/arch/arm/mach-omap/Kconfig 2022-08-10 08:49:07.000000000 +0200 +++ b/arch/arm/mach-omap/Kconfig 2022-09-13 08:33:01.214045750 +0200 @@ -180,6 +180,12 @@ help Say Y here if you are using a am335x based Phytecs SOM +config MACH_MIU + bool "KBS Industrieelektronik GmbH PTF-MIU" + select ARCH_AM33XX + help + Say Y here if you are using KBS Industrieelektronik GmbH PTF-MIU device + config MACH_VSCOM_BALTOS bool "VScom Baltos Devices" select ARCH_AM33XX diff -ruPN a/images/Makefile.am33xx b/images/Makefile.am33xx --- a/images/Makefile.am33xx 2022-08-10 08:49:07.000000000 +0200 +++ b/images/Makefile.am33xx 2022-09-13 07:35:58.887910463 +0200 @@ -136,6 +136,15 @@ FILE_barebox-am33xx-beaglebone-mlo.img = start_am33xx_beaglebone_sram.pblb.mlo am33xx-mlo-$(CONFIG_MACH_BEAGLEBONE) += barebox-am33xx-beaglebone-mlo.img +pblb-$(CONFIG_MACH_MIU) += start_miu_sdram +FILE_barebox-miu.img = start_miu_sdram.pblb +am33xx-barebox-$(CONFIG_MACH_MIU) += barebox-miu.img + +pblb-$(CONFIG_MACH_MIU) += start_miu_sram +FILE_barebox-miu-mlo.img = start_miu_sram.pblb.mlo +am33xx-mlo-$(CONFIG_MACH_MIU) += barebox-miu-mlo.img + + pblb-$(CONFIG_MACH_VSCOM_BALTOS) += start_am33xx_baltos_sdram FILE_barebox-am33xx-baltos.img = start_am33xx_baltos_sdram.pblb am33xx-barebox-$(CONFIG_MACH_VSCOM_BALTOS) += barebox-am33xx-baltos.img