M. Feser KBS GmbH Date: 09.11.2017 This patch adds the devicetree for PTF-MIU ------------------------------------------------------------------------- diff -ruPN a/arch/arm/boot/dts/miu.dts b/arch/arm/boot/dts/miu.dts --- a/arch/arm/boot/dts/miu.dts 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boot/dts/miu.dts 2016-01-21 13:27:08.687792666 +0100 @@ -0,0 +1,694 @@ +/* + * PTF-MIU device tree + * Copyright (C) 2016 M. Feser + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "PTF-MIU"; + compatible = "kbs,miu", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + operating-points = < + // kHZ uV + 1000000 1325000 // 1.325 nom + 800000 1260000 // 1.260 nom + 720000 1200000 // 1.200 nom + 500000 1100000 // 1.100 nom + 300000 950000 // 0.950 nom + >; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; // 512 MB + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + ldo33: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "ldo33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + switches { + compatible = "gpio-keys-polled"; + pinctrl-names = "default"; + pinctrl-0 = <&switch_pins>; + poll-interval = <100>; + + switch-mode0 { + label = "mode0"; + linux,code = <1>; // Key = ESC + gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + }; + + switch-mode1 { + label = "mode1"; + linux,code = <2>; // Key = 1 + gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-blue { + label = "blue"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-red { + label = "red"; + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + spi1_mux_switch { + compatible = "mux-switch"; + pinctrl-names = "default", "swd"; + pinctrl-0 = <&spi1_pins>; + pinctrl-1 = <&swd_pins>; + status = "okay"; + }; + + slot0_mux_switch { + compatible = "mux-switch"; + pinctrl-names = "default", "ptf"; + pinctrl-0 = <&slot0_default_pins>; + pinctrl-1 = <&slot0_ptfmod_pins>; + status = "okay"; + }; + + slot1_mux_switch { + compatible = "mux-switch"; + pinctrl-names = "default", "ptf"; + pinctrl-0 = <&slot1_default_pins>; + pinctrl-1 = <&slot1_ptfmod_pins>; + status = "okay"; + }; + + slot2_mux_switch { + compatible = "mux-switch"; + pinctrl-names = "default", "ptf"; + pinctrl-0 = <&slot2_default_pins>; + pinctrl-1 = <&slot2_ptfmod_pins>; + status = "okay"; + }; + + slot3_mux_switch { + compatible = "mux-switch"; + pinctrl-names = "default", "ptf"; + pinctrl-0 = <&slot3_default_pins>; + pinctrl-1 = <&slot3_ptfmod_pins>; + status = "okay"; + }; +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&sysboot_pins &input_pins>; + + sysboot_pins: pinmux_sysboot_pins { + pinctrl-single,pins = < + 0x0D8 (PIN_OUTPUT | MUX_MODE7) // lcd_data14.gpio0_10 -> EMMC_NRST + 0x0DC (PIN_OUTPUT | MUX_MODE7) // lcd_data15.gpio0_11 -> EXP_NRST + 0x21C (PIN_OUTPUT | MUX_MODE7) // usb0_drvvbus.gpio0_18 -> SYSBOOT_DIS + >; + }; + + input_pins: pinmux_input_pins { + pinctrl-single,pins = < + 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) // gpmc_ben1.gpio1_28 -> PMIC_INT + 0x1AC (PIN_INPUT_PULLUP | MUX_MODE7) // mcasp0_ahclkx.gpio3_21 -> GP_INPUT + >; + }; + + switch_pins: pinmux_switch_pins { + pinctrl-single,pins = < + 0x0C8 (PIN_INPUT_PULLUP | MUX_MODE7) // lcd_data10.gpio2_16 -> MODE0 + 0x0CC (PIN_INPUT_PULLUP | MUX_MODE7) // lcd_data11.gpio2_17 -> MODE1 + >; + }; + + led_pins: pinmux_led_pins { + pinctrl-single,pins = < + 0x0D0 (PIN_OUTPUT | MUX_MODE7) // lcd_data12.gpio0_8 + 0x0D4 (PIN_OUTPUT | MUX_MODE7) // lcd_data13.gpio0_9 + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) // i2c0_sda.i2c0_sda + 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) // i2c0_scl.i2c0_scl + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x168 (PIN_INPUT_PULLUP | MUX_MODE0) // uart0_ctsn.i2c1_sda + 0x16C (PIN_INPUT_PULLUP | MUX_MODE0) // uart0_rtsn.i2c1_scl + >; + }; + + spi0_pins: pinmux_spi0_pins { + pinctrl-single,pins = < + // SPI clock pin has to be configured in rx active mode ! + 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) // spi0_sclk.spi0_sclk + 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) // spi0_d0.spi0_d0 -> MISO + 0x158 (PIN_OUTPUT | MUX_MODE0) // spi0_d1.spi0_d1 -> MOSI + 0x15C (PIN_OUTPUT | MUX_MODE0) // spi0_cs0.spi0_cs0 -> SPI0_CS0 + 0x0AC (PIN_OUTPUT | MUX_MODE7) // lcd_data3.gpio2_9 -> SPI0_CS1 + 0x0A8 (PIN_OUTPUT | MUX_MODE7) // lcd_data2.gpio2_8 -> 7SEG_STROBE + >; + }; + + spi1_pins: pinmux_spi1_pins { + pinctrl-single,pins = < + // SPI clock pin has to be configured in rx active mode ! + 0x190 (PIN_INPUT_PULLUP | MUX_MODE3) // mcasp0_aclkx.spi1_sclk + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE3) // mcasp0_fsx.spi1_d0 -> MISO + 0x198 (PIN_OUTPUT | MUX_MODE3) // mcasp0.axr0.spi1_d1 -> MOSI + >; + }; + + spi1cs_pins: pinmux_spi1cs_pins { + pinctrl-single,pins = < + 0x0B0 (PIN_OUTPUT | MUX_MODE7) // lcd_data4.gpio2_10 -> SPI1_CS0 + 0x0B4 (PIN_OUTPUT | MUX_MODE7) // lcd_data5.gpio2_11 -> SPI1_CS1 + 0x0B8 (PIN_OUTPUT | MUX_MODE7) // lcd_data6.gpio2_12 -> SPI1_CS2 + 0x0BC (PIN_OUTPUT | MUX_MODE7) // lcd_data7.gpio2_13 -> SPI1_CS3 + >; + }; + + swd_pins: pinmux_swd_pins { + pinctrl-single,pins = < + 0x190 (PIN_OUTPUT | MUX_MODE7) // mcasp0_aclkx.gpio3_14 -> CLK + 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mcasp0_fsx.gpio3_15 -> MISO + 0x198 (PIN_OUTPUT | MUX_MODE7) // mcasp0.axr0.gpio3_16 -> MOSI + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) // uart0_rxd.uart0_rxd + 0x174 (PIN_OUTPUT | MUX_MODE0) // uart0_txd.uart0_txd + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) // uart1_rxd.uart1_rxd + 0x184 (PIN_OUTPUT | MUX_MODE0) // uart1_txd.uart1_txd + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + 0x12C (PIN_INPUT_PULLUP | MUX_MODE1) // mii1_tx_clk.uart2_rxd + 0x130 (PIN_OUTPUT | MUX_MODE1) // mii1_rx_clk.uart2_txd + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + 0x134 (PIN_INPUT_PULLUP | MUX_MODE1) // mii1_rxd3.uart3_rxd + 0x138 (PIN_OUTPUT | MUX_MODE1) // mii1_rxd2.uart3_txd + >; + }; + + uart4_pins: pinmux_uart4_pins { + pinctrl-single,pins = < + 0x11C (PIN_INPUT_PULLUP | MUX_MODE3) // mii1_txd3.uart4_rxd + 0x120 (PIN_OUTPUT | MUX_MODE3) // mii1_txd2.uart4_txd + >; + }; + + uart5_pins: pinmux_uart5_pins { + pinctrl-single,pins = < + 0x0C4 (PIN_INPUT_PULLUP | MUX_MODE4) // lcd_data9.uart5_rxd + 0x0C0 (PIN_OUTPUT | MUX_MODE4) // lcd_data8.uart5_txd + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + // ETH 1 + 0x10C (PIN_INPUT | MUX_MODE1) // mii1_crs.rmii1_crs_dv + 0x110 (PIN_INPUT | MUX_MODE1) // mii1_rxer.rmii1_rxer + 0x114 (PIN_OUTPUT | MUX_MODE1) // mii1_txen.rmii1_txen + 0x124 (PIN_OUTPUT | MUX_MODE1) // mii1_txd1.rmii1_txd1 + 0x128 (PIN_OUTPUT | MUX_MODE1) // mii1_txd0.rmii1_txd0 + 0x13C (PIN_INPUT | MUX_MODE1) // mii1_rxd1.rmii1_rxd1 + 0x140 (PIN_INPUT | MUX_MODE1) // mii1_rxd0.rmii1_rxd0 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) // rmii1_refclk.rmii1_refclk + + // ETH 2 + 0x070 (PIN_INPUT | MUX_MODE3) // gpmc_wait0.rmii2_crs_dv + 0x074 (PIN_INPUT | MUX_MODE3) // gpmc_wpn.rmii2_rxer + 0x040 (PIN_OUTPUT | MUX_MODE3) // gpmc_a0.rmii2_txen + 0x050 (PIN_OUTPUT | MUX_MODE3) // gpmc_a4.rmii2_txd1 + 0x054 (PIN_OUTPUT | MUX_MODE3) // gpmc_a5.rmii2_txd0 + 0x068 (PIN_INPUT | MUX_MODE3) // gpmc_a10.rmii2_rxd1 + 0x06C (PIN_INPUT | MUX_MODE3) // gpmc_a11.rmii2_rxd0 + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) // mii1_col.rmii2_refclk + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + // ETH 1 sleep + 0x10C (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_crs.rmii1_crs_dv + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_rxer.rmii1_rxer + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_txen.rmii1_txen + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_txd1.rmii1_txd1 + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_txd0.rmii1_txd0 + 0x13C (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_rxd1.rmii1_rxd1 + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_rxd0.rmii1_rxd0 + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) // rmii1_refclk.rmii1_refclk + + // ETH 2 sleep + 0x070 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_wait0.rmii2_crs_dv + 0x074 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_wpn.rmii2_rxer + 0x040 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a0.rmii2_txen + 0x050 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a4.rmii2_txd1 + 0x054 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a5.rmii2_txd0 + 0x068 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a10.rmii2_rxd1 + 0x06C (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a11.rmii2_rxd0 + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_col.rmii2_refclk + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + // MDIO + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) // mdio_data.mdio_data + 0x14C (PIN_OUTPUT_PULLUP | MUX_MODE0) // mdio_clk.mdio_clk + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + // MDIO sleep + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14C (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0x160 (PIN_INPUT | MUX_MODE7) // spi0_cs1.gpio0_6 + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) // gpmc_csn1.mmc1_clk + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) // gpmc_csn2.mmc1_cmd + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad0.mmc1_dat0 + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad1.mmc1_dat1 + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad2.mmc1_dat2 + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad3.mmc1_dat3 + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad4.mmc1_dat4 + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad5.mmc1_dat5 + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad6.mmc1_dat6 + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) // gpmc_ad7.mmc1_dat7 + >; + }; +}; + +#include "miu-slots.dtsi" + +&gpio0 { + ti,no-reset-on-init; +}; + +&gpio1 { + ti,no-reset-on-init; +}; + +&gpio2 { + ti,no-reset-on-init; +}; + +&gpio3 { + ti,no-reset-on-init; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins>; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&cppi41dma { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2D { + reg = <0x2D>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + cs-gpios = <0>, <&gpio2 9 0>, <&gpio2 8 0>; + status = "okay"; + + spidev0@0 { + compatible = "linux,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + }; + + sysnvm@1 { + compatible = "atmel,at25"; + reg = <1>; + spi-max-frequency = <10000000>; + + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + + segdsp@2 { + compatible = "linux,spidev"; + reg = <2>; + spi-max-frequency = <10000000>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1cs_pins>; + cs-gpios = <&gpio2 10 0>, <&gpio2 11 0>, <&gpio2 12 0>, <&gpio2 13 0>, + <&gpio0 7 0>, <&gpio3 17 0>, <&gpio1 17 0>, <&gpio2 24 0>; + status = "okay"; + + slot0nvm@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <10000000>; + + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + + slot1nvm@0 { + compatible = "atmel,at25"; + reg = <1>; + spi-max-frequency = <10000000>; + + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + + slot2nvm@0 { + compatible = "atmel,at25"; + reg = <2>; + spi-max-frequency = <10000000>; + + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + + slot3nvm@0 { + compatible = "atmel,at25"; + reg = <3>; + spi-max-frequency = <10000000>; + + pagesize = <32>; + size = <8192>; + address-width = <16>; + }; + + slot0spidev@0 { + compatible = "linux,spidev"; + reg = <4>; + spi-max-frequency = <10000000>; + }; + + slot1spidev@0 { + compatible = "linux,spidev"; + reg = <5>; + spi-max-frequency = <10000000>; + }; + + slot2spidev@0 { + compatible = "linux,spidev"; + reg = <6>; + spi-max-frequency = <10000000>; + }; + + slot3spidev@0 { + compatible = "linux,spidev"; + reg = <7>; + spi-max-frequency = <10000000>; + }; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rmii"; +}; + +&phy_sel { + rmii-clock-ext; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + bus-width = <4>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <&ldo33>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + bus-width = <8>; + ti,non-removable; + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; + +&rtc { + clocks = <&clk_32768_ck>; + clock-names = "ext-clk"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + // VDD_MPU voltage limits 0.950V - 1.325V with +/-4% tolerance + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + // VDD_CORE voltage limits 0.950V - 1.100V with +/-4% tolerance + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1137500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff -ruPN a/arch/arm/boot/dts/miu-slots.dtsi b/arch/arm/boot/dts/miu-slots.dtsi --- a/arch/arm/boot/dts/miu-slots.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ b/arch/arm/boot/dts/miu-slots.dtsi 2015-06-29 16:08:50.000000000 +0200 @@ -0,0 +1,112 @@ +/* + * PTF-MIU slots device tree include + * Copyright (C) 2016 M. Feser + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +&am33xx_pinmux { +// Slot 0 + slot0_default_pins: pinmux_slot0_default_pins { + pinctrl-single,pins = < + 0x048 (PIN_OUTPUT | MUX_MODE7) // gpmc_a2.gpio1_18 -> GPO_00 + 0x090 (PIN_INPUT_PULLUP | MUX_MODE7) // gpmc_advn_ale.gpio2_2 -> GPIO_01 + 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) // ecap0_in_pwm0_out.gpio0_7 -> GPIO_02 + 0x1B0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // xdma_event_intr0.gpio0_19 -> GPIO_03 + 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mii1_rx_dv.gpio3_4 -> GPIO_04 + 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mcasp0_aclkr.gpio3_18 -> GPIO_05 + >; + }; + + slot0_ptfmod_pins: pinmux_slot0_ptfmod_pins { + pinctrl-single,pins = < + 0x048 (PIN_OUTPUT | MUX_MODE7) // gpmc_a2.gpio1_18 -> SWD_ENAN + 0x090 (PIN_OUTPUT | MUX_MODE7) // gpmc_advn_ale.gpio2_2 -> SWD_WRN + 0x164 (PIN_OUTPUT | MUX_MODE7) // ecap0_in_pwm0_out.gpio0_7 -> SPI_CS + 0x1B0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // xdma_event_intr0.gpio0_19 -> IPC_REQ + 0x118 (PIN_OUTPUT | MUX_MODE7) // mii1_rx_dv.gpio3_4 -> IPC_RDY + 0x1A0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // mcasp0_aclkr.gpio3_18 -> PGOOD + >; + }; + +// Slot 1 + slot1_default_pins: pinmux_slot1_default_pins { + pinctrl-single,pins = < + 0x04C (PIN_OUTPUT | MUX_MODE7) // gpmc_a3.gpio1_19 -> GPO_10 + 0x09C (PIN_INPUT_PULLUP | MUX_MODE7) // gpmc_ben0_cle.gpio2_5 -> GPIO_11 + 0x19C (PIN_INPUT_PULLUP | MUX_MODE7) // mcasp0_ahclkr.gpio3_17 -> GPIO_12 + 0x1B4 (PIN_INPUT_PULLDOWN | MUX_MODE7) // xdma_event_intr1.gpio0_20 -> GPIO_13 + 0x060 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a8.gpio1_24 -> GPIO_14 + 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a9.gpio1_25 -> GPIO_15 + >; + }; + + slot1_ptfmod_pins: pinmux_slot1_ptfmod_pins { + pinctrl-single,pins = < + 0x04C (PIN_OUTPUT | MUX_MODE7) // gpmc_a3.gpio1_19 -> SWD_ENAN + 0x09C (PIN_OUTPUT | MUX_MODE7) // gpmc_ben0_cle.gpio2_5 -> SWD_WRN + 0x19C (PIN_OUTPUT | MUX_MODE7) // mcasp0_ahclkr.gpio3_17 -> SPI_CS + 0x1B4 (PIN_INPUT_PULLDOWN | MUX_MODE7) // xdma_event_intr1.gpio0_20 -> IPC_REQ + 0x060 (PIN_OUTPUT | MUX_MODE7) // gpmc_a8.gpio1_24 -> IPC_RDY + 0x064 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a9.gpio1_25 -> PGOOD + >; + }; + +// Slot 2 + slot2_default_pins: pinmux_slot2_default_pins { + pinctrl-single,pins = < + 0x0A0 (PIN_OUTPUT | MUX_MODE7) // lcd_data0.gpio2_6 -> GPO_20 + 0x098 (PIN_INPUT_PULLUP| MUX_MODE7) // gpmc_wen.gpio2_4 -> GPIO_21 + 0x044 (PIN_INPUT_PULLUP | MUX_MODE7) // gpmc_a1.gpio1_17 -> GPIO_22 + 0x058 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a6.gpio1_22 -> GPIO_23 + 0x05C (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a7.gpio1_23 -> GPIO_24 + 0x07C (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_csn0.gpio1_29 -> GPIO_25 + >; + }; + + slot2_ptfmod_pins: pinmux_slot2_ptfmod_pins { + pinctrl-single,pins = < + 0x0A0 (PIN_OUTPUT | MUX_MODE7) // lcd_data0.gpio2_6 -> SWD_ENAN + 0x098 (PIN_OUTPUT | MUX_MODE7) // gpmc_wen.gpio2_4 -> SWD_WRN + 0x044 (PIN_OUTPUT | MUX_MODE7) // gpmc_a1.gpio1_17 -> SPI_CS + 0x058 (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_a6.gpio1_22 -> IPC_REQ + 0x05C (PIN_OUTPUT | MUX_MODE7) // gpmc_a7.gpio1_23 -> IPC_RDY + 0x07C (PIN_INPUT_PULLDOWN | MUX_MODE7) // gpmc_csn0.gpio1_29 -> PGOOD + >; + }; + +// Slot 3 + slot3_default_pins: pinmux_slot3_default_pins { + pinctrl-single,pins = < + 0x0A4 (PIN_OUTPUT | MUX_MODE7) // lcd_data1.gpio2_7 -> GPO_30 + 0x094 (PIN_INPUT_PULLUP | MUX_MODE7) // gpmc_oen_ren.gpio2_3 -> GPIO_31 + 0x0E8 (PIN_INPUT_PULLUP | MUX_MODE7) // lcd_pclk.gpio2_24 -> GPIO_32 + 0x0E0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // lcd_vsync.gpio2_22 -> GPIO_33 + 0x0E4 (PIN_INPUT_PULLDOWN | MUX_MODE7) // lcd_hsync.gpio2_23 -> GPIO_34 + 0x0EC (PIN_INPUT_PULLDOWN | MUX_MODE7) // lcd_ac_bias_en.gpio2_25 -> GPIO_35 + >; + }; + + slot3_ptfmod_pins: pinmux_slot3_ptfmod_pins { + pinctrl-single,pins = < + 0x0A4 (PIN_OUTPUT | MUX_MODE7) // lcd_data1.gpio2_7 -> SWD_ENAN + 0x094 (PIN_OUTPUT | MUX_MODE7) // gpmc_oen_ren.gpio2_3 -> SWD_WRN + 0x0E8 (PIN_OUTPUT | MUX_MODE7) // lcd_pclk.gpio2_24 -> SPI_CS + 0x0E0 (PIN_INPUT_PULLDOWN | MUX_MODE7) // lcd_vsync.gpio2_22 -> IPC_REQ + 0x0E4 (PIN_OUTPUT | MUX_MODE7) // lcd_hsync.gpio2_23 -> IPC_RDY + 0x0EC (PIN_INPUT_PULLDOWN | MUX_MODE7) // lcd_ac_bias_en.gpio2_25 -> PGOOD + >; + }; +};