diff -ruPN a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
--- a/drivers/net/phy/smsc.c	2015-05-05 18:39:05.000000000 +0200
+++ b/drivers/net/phy/smsc.c	2015-06-19 15:36:34.812297058 +0200
@@ -57,6 +57,32 @@
 	return smsc_phy_ack_interrupt(phydev);
 }
 
+static int lan87xx_config_init(struct phy_device *phydev)
+{
+	/*
+	 * Make sure the EDPWRDOWN bit is NOT set. Setting this bit on
+	 * LAN8710/LAN8720 PHY causes the PHY to misbehave, likely due
+	 * to a bug on the chip.
+	 *
+	 * When the system is powered on with the network cable being
+	 * disconnected all the way until after ifconfig ethX up is
+	 * issued for the LAN port with this PHY, connecting the cable
+	 * afterwards does not cause LINK change detection, while the
+	 * expected behavior is the Link UP being detected.
+	 */
+	int rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
+	if (rc < 0)
+		return rc;
+
+	rc &= ~MII_LAN83C185_EDPWRDOWN;
+
+	rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, rc);
+	if (rc < 0)
+		return rc;
+
+	return smsc_phy_ack_interrupt(phydev);
+}
+
 static int smsc_phy_reset(struct phy_device *phydev)
 {
 	int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES);
@@ -85,49 +111,41 @@
 	return 0;
 }
 
+static int lan87xx_reset(struct phy_device *phydev)
+{
+	int rc = phy_read(phydev, MII_LAN83C185_SPECIAL_MODES);
+	if (rc < 0)
+		return rc;
+
+	int timeout = 50000;
+
+  /* set "all capable" mode and reset the phy */
+  rc |= MII_LAN83C185_MODE_ALL;
+  phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc);
+  phy_write(phydev, MII_BMCR, BMCR_RESET);
+
+  /* wait end of reset (max 500 ms) */
+  do {
+    udelay(10);
+    if (timeout-- == 0)
+      return -1;
+    rc = phy_read(phydev, MII_BMCR);
+  } while (rc & BMCR_RESET);
+	return 0;
+}
+
 static int lan911x_config_init(struct phy_device *phydev)
 {
 	return smsc_phy_ack_interrupt(phydev);
 }
 
-/*
- * The LAN8710/LAN8720 requires a minimum of 2 link pulses within 64ms of each
- * other in order to set the ENERGYON bit and exit EDPD mode.  If a link partner
- * does send the pulses within this interval, the PHY will remained powered
- * down.
- *
- * This workaround will manually toggle the PHY on/off upon calls to read_status
- * in order to generate link test pulses if the link is down.  If a link partner
- * is present, it will respond to the pulses, which will cause the ENERGYON bit
- * to be set and will cause the EDPD mode to be exited.
- */
 static int lan87xx_read_status(struct phy_device *phydev)
 {
 	int err = genphy_read_status(phydev);
 
 	if (!phydev->link) {
-		/* Disable EDPD to wake up PHY */
-		int rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
-		if (rc < 0)
-			return rc;
-
-		rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
-			       rc & ~MII_LAN83C185_EDPWRDOWN);
-		if (rc < 0)
-			return rc;
-
 		/* Sleep 64 ms to allow ~5 link test pulses to be sent */
 		msleep(64);
-
-		/* Re-enable EDPD */
-		rc = phy_read(phydev, MII_LAN83C185_CTRL_STATUS);
-		if (rc < 0)
-			return rc;
-
-		rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS,
-			       rc | MII_LAN83C185_EDPWRDOWN);
-		if (rc < 0)
-			return rc;
 	}
 
 	return err;
@@ -237,8 +255,8 @@
 	/* basic functions */
 	.config_aneg	= genphy_config_aneg,
 	.read_status	= lan87xx_read_status,
-	.config_init	= smsc_phy_config_init,
-	.soft_reset	= smsc_phy_reset,
+	.config_init	= lan87xx_config_init,
+	.soft_reset	= lan87xx_reset,
 
 	/* IRQ related */
 	.ack_interrupt	= smsc_phy_ack_interrupt,